Phase-locked loops are used in a variety of applications such as clock recovery, frequency and phase modulation, and frequency synthesizers. Designs use either a voltage-controlled oscillator (VCO) or a current-controlled oscillator (CCO) with an accompanying voltage-to-current (V2I) converter as a central design element of the phase-locked loop, whereby the oscillator produces an output frequency proportional to its input voltage (in the case of a VCO) or current (in the case of a CCO).
A wide frequency range is needed for covering the wide frequency range clocking requirements of modern CPUs and system-on-chip (SOC) applications. A typical drawback of the oscillator is its uncertainty in output frequency to the applied input due to integrated circuit process variations. This leads to the need for an oscillator having a large gain (Kvco) to provide the desired frequencies. However, the large gain also has the effect of producing a large variation in the output frequency in response to any noise in the applied input voltage, also known as phase noise or jitter. This phase noise at the oscillator output is undesirable as it limits the purity of the output signal. A low Kvco is needed to minimize the noise transfer from the input (i.e., reference clock).
CCO-based PLLs have been proposed but also have very high Kvco (e.g., 10 GHz/V or more), which undesirably pass noise and also require a large loop filter capacitors, which has area penalties, or low charge-pump current for a PLL bandwidth range requirement. The low charge pump current makes the oscillator more sensitive to charge pump current mismatch from charge injection, displacement current, device leakage, etc.
Improved CCO-based PLL circuits are desired.